AN4300 datasheet(21/40 Pages) STMICROELECTRONICS

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AN4300

MCU initialization

Figure 12. PLL initialization function

The PA[0] pin is configured as Clock output in order to verify the clock bus frequency

provided by the PLL. The CGM module allows to tune the dividers in order to provide a clock

source of 12MHz starting from an external oscillator of 40 MHz.

4.2

DSPI configuration

The following function allows to initialize the DSPI module used for the SPI transmission.

It configures the DSPI_0 as master and the following pins as:

•

Pad PA[12] as DSPI_0 SIN (Serial input)

• Pad PA[13] as DSPI_0 SOUT (Serial output)

• Pad PA[14] as DSPI_0 SCK (Serial Communication Clock)

• Pad PA[15] as DSPI_0 PCS0 (Peripheral Chip Select_0)

• Pad PF[10] as DSPI_0 PCS1 (Peripheral Chip Select_1)

• Pad PF[11] as DSPI_0 PCS2 (Peripheral Chip Select_2)

• Pad PE[06] as DSPI_0 PCS3 (Peripheral Chip Select_3)

The CTAR register defines the following parameters:

• Set Double Baud rate disabled

• Frame size equal to 16

• Baud Rate Prescaler value equal to 3

• Baud Rate Scaler equal to 4

• Delay after Transfer Scaler equal to 32

AN4300 数据表(PDF) 21 Page - STMicroelectronics