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AN4417

Z4 Core exception overview

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Z4 Core exception overview

Z4 Core used on SPC564Axx/SPC56ELxx devices contains many exception sources and

sixteen interrupts to service them. Multiple exception sources can be mapped to one

interrupt handler where few supportive status registers provide flags to find the cause of the

exception in the handler.

Detailed list of the exception causes and their mapping to interrupt handlers is found in the

Z4 Core Reference Manual (see Section Appendix B: Reference documents).

This chapter gives an overview of machine check interrupt that is utilized for several

important fault states of SPC564Axx/SPC56ELxx devices.

1.1

Machine check interrupt (IVOR1)

Machine check interrupt is a handler that services multiple fault events that may occur

during runtime code execution.

This interrupt is used to handle various faults generated by peripherals in the

SPC564Axx/SPC56ELxx devices, like MPU protection fault, 2b ECC error in the Flash or

RAM memory etc. The reason is that most of the faults are signaled back as external bus

error situation during the CPU-Submodule bus transaction.

1.1.1

Machine check registers

Z4 core implements few machine check status registers that are updated upon the

exception event with some constraints stated in the Z4 Core Reference Manual (see

Section Appendix B: Reference documents). These registers are used to find the source of

the exception and based on, it is decided how to solve it.

Table 1. Machine check interrupt causes

Interrupt type

Exception conditions

Machine check

-NMI

-ISI, ITLB, Error on first instruction fetch for an exception handler

-Parity Error signaled on cache access

-External bus error