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AN4441 数据表(PDF) 2 Page - STMicroelectronics

部件名 AN4441
功能描述  Start time of the RHFLVDS32A receiver
PDF  5 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN4441 数据表(HTML) 2 Page - STMicroelectronics

  AN4441 Datasheet HTML 1Page - STMicroelectronics AN4441 Datasheet HTML 2Page - STMicroelectronics AN4441 Datasheet HTML 3Page - STMicroelectronics AN4441 Datasheet HTML 4Page - STMicroelectronics AN4441 Datasheet HTML 5Page - STMicroelectronics  
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Data transmission description
AN4441
2/5
DocID025920 Rev 1
1
Data transmission description
The
rad-hard,
quad
RHFLVDS31A
driver
and
RHFLVDS32A
receiver
of
STMicroelectronics are designed to be used in cold spare mode. This means that a spare
operating unit can be connected in parallel to a main operating unit for all pins except Vcc.
The Vcc power input of each cold spare unit is tied to ground. In this case, the cold spare
feature guarantees that no change in performance occurs compared to the situation when
only a single operating unit is used. In Figure 1, the spare operating units are
RHFLVDS31A_2 and RHFLVDS32A_2 and the main operating units are RHFLVDS31A_1
and RHFLVDS32A_1.
The suggested data transmission example uses only one of the four cells of each driver
and receiver device. The cold spare units RHFLVDS31A_2 and RHFLVDS32A_2 are
connected through transmission lines TL2 and TL3. These lines carry the differential data
to a target destination of 100 Ω. The data comprise a PRBS9 signal running at 200 MHz.
By switching the enable control at a convenient rate on the receiver side of Figure 1, it is
possible to obtain a full screening of the output behavior (single-ended CMOS). To achieve
this, a 100 ns square signal is applied on the \G input pin of the two receivers
(RHFLVDS32A_2 and RHFLVDS32A_1).
The receiver output is prepared for a high impedance state when it is disabled. Output
matching is performed thanks to a simple voltage divider which uses a 50 Ω oscilloscope
input load. Correct coaxial lengths are included in the measurement chain, to control for
delay compensations (i.e. the sum of track delays in the order of 800 ps on the board being
used). This implementation is necessary to synchronize the divided output (Vo trace), as
well as to display correct timings.
Figure 2 shows:
\G (upper trace): a perfect replica of the applied enable control of the receivers
(RHFLVDS32A_2 and RHFLVDS32A_1).
Vo (lower trace): a fraction of the output signal, recorded using infinite persistence
mode of the oscilloscope to display the PRBS9 data better.
Figure 2: Start time of the RHFLVDS32A_2 and RHFLVDS32A_1 receivers
1.
The hatched vertical bars show ΔT = 3.5 ns.



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