RPD functionality

AN2340

2/10

1

RPD functionality

RPD is a dual purpose dedicated pin. This section covers its functionality.

1.1

System reset and startup

Several ST10 reset events that may occur are summarized in the following table:

Therefore, roughly, the RPD pin level distinguishes between an asynchronous (low level)

and a synchronous reset (high level). The main difference between these two kinds of reset

is that the first immediately cancels pending internal hold states and if any, it aborts all

internal/external bus cycles whereas in the synchronous reset, after RSTIN level is

detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses,

during which pending internal hold states are cancelled and the current internal access

cycle, if any, is completed. For this reason, if an asynchronous reset occurs during a read or

write phase in internal memories, the content of the memory itself could be corrupted. To

avoid this, synchronous reset usage is strongly recommended.

However, the asynchronous reset must be used during the power-on of the device.

Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to

stabilized clock signal to detect an asynchronous reset and is therefore suitable for power-

on conditions.

On the contrary, the reset state machine needs a stabilized clock to operate correctly.

According to the length of pulse on RSTIN, the synchronous reset may be recognized as

Table 1.

Reset event definition

Reset Source

1.

Flags can be read in the WDTCON register

RPD

Status

Conditions

Power-on reset

PONR

Low

Power-on

Asynchronous hardware

reset

LHWR

Low

Synchronous long

hardware reset

High

Synchronous short

hardware reset

SHWR

High

Watchdog timer reset

WDTR

(2)

2.

The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD

low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated.

WDT overflow

Software reset

SWR

(2)

SRST instruction execution