AN2791

Virtual current control loop on the Q1, Q2 channels of Root Part Number 1

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Virtual current control loop on the Q1, Q2 channels of

Root Part Number 1

Root Part Number 1, aimed to understand the limits of a virtual current control loop on the

considered same load conditions, that is, for both the regulated and unregulated channels of

the Root Part Number 1, we considered same coils, same INLET valves. Furthermore, to

balance the difference of PWM signal frequency on the Root Part Number 1 channels, the

wheeling diodes have been used to link the channel output and Vbat. As free-wheeling

diode we have considered the ST power Shottky diodes 1N5817.

Figure 9.

Evaluation of the VCCL on the L9352B unregulated channels: first test

condition block scheme

As first operative condition for our tests (see Figure 9) we can refer to the following data:

●

INLET valve opening/closing frequency of 1Hz

●

for the first 450 ms, duty-cycle = 0.1 %

●

for the next 50 ms, duty-cycle = 90 %

●

for the last 500 ms, duty-cycle =[ 15:10:75] %

The Table 2 shows the results related to this first operative condition that we considered for

our tests. As we can see in the last four columns, the difference between the mean current

on the load driven by the unregulated channel and the mean current on the load driven by

the regulated channel reduces as the set-point, that is, the duty of the hold phase increases.

b.

Take into account that the ideal frequency of the output PWM signal of the current regulated channels (i.e. Q3,

Q4) is the (clock frequency)/64, that is, 3.9 kHz for a clock frequency of 250 kHz.