Methodology

AN934

4/14

Doc ID 6393 Rev 4

Methodology

oscillator with a nominal frequency of 32.768 kHz. The crystal is mounted in either a 600 mil

DIP CAPHAT™ package, 600 mil DIP hybrid, 300mil SOIC embedded crystal, or in a

accurate within ±1.53 minutes (±35 ppm - parts per million) per month at 25 °C without

calibration.

Two sources of clock error are:

●

temperature variation

●

crystal variation

As mentioned previously, most clock chips compensate for crystal frequency and

temperature shift error with cumbersome “trim” capacitors. The TIMEKEEPER design

employs periodic counter correction. The digital calibration circuit adds or subtracts counts

from the oscillator divider circuit at the 256 Hz stage (see Figure 2).

Figure 3 shows how extra clock pulses are added (by clock splitting) or removed (by clock

blanking). The number of times the pulses are split (added during positive calibration) or

blanked (subtracted during negative calibration) depends upon the value that has been

loaded into the least significant five bits of the control register. Adding counts speeds the

clock up while subtracting counts slows the clock down.

Figure 2.

Oscillator divider chain

Figure 3.

Clock splitting and clock blanking

Calibration

Circuitry

AI02800

Low

Current

Oscillator

32768Hz

512Hz Output

for Frequency Test

256Hz

1Hz Signal

Clock

Registers

64 Minute

Cycle

div 64

div 2

AI02801

No Calibration

Positive Clock Calibration

Negative Clock Calibration