AN1879

Description

1.4

RAM clear data

Depending on the process technology used to manufacture the external SRAM, clearing

the memory may require varying durations of negative potential on the VCC pin. The

M41ST87W device allows the user to program the time needed for their particular

application. The control bits CLRPW0 and CLRPW1, located in the day register, determine

the duration of the tCLR pulse width during a tamper event (see Figure 2: "Tamper output

timing" ). Thus, users can control the voltage and duration of the negative pulse enabling

them to configure the circuit for many different LPSRAMs.

Figure 2: Tamper output timing

Note: see M41ST87W datasheet for timing details.

1.5

Tamper timestamp

When the device is tampered with, and regardless of which tamper occurs first, a time

stamp freezing the update of the clock registers will occur to let the user know when it was

tampered with. The tamper bits (TB1 or TB2 in the flag register) will be set immediately.

Therefore, when tampering occurs, the user may elect to first read the time registers to

determine exactly when the tamper event occurred, then read the flag register to see which

tamper condition was triggered. The clock will update to the current time after resetting the

TEB bit in the tamper registers. The appropriate TEB bit must always be reset to '0' in order

backup.

DocID010159 Rev 5

5/8

TP

CLR

VOUT

RST

Tamper

Event

(TB Bit set)

High-Z

t

t

t

ECON

IRQ/OUT

High-Z

rec

CLR

CLRD