AN2159

Data processing

Doc ID 11400 Rev 3

13/23

5

Data processing

5.1

Reading process

As told before, to start a SPI communication with STPMxx to read new values of registers, it

is necessary to apply a latching phase first. Then a shifting phase starts, as reported in

Figure 4.

After that, 32 pulses of serial clocks needs to be applied to pin SCL in order to read the DAP

register. If additional 32 pulses are applied to pin SCL, the DRP register is read. At this point

there are two possibilities. Either reading is continued by applying 32 clocks per register until

all registers of interest are read or a precharge command is applied first (8 pulses to pin

SCLNLC while SYN=0 and SDA=1) which moves an internal read pointer to register DEV

which effectively skips DSP and DFP registers, and then reading may be continued.

It is up to an application to decide how many records should be read out from the device.

After all registers are read, SCS can be returned to idle state which ends the shifting phase.

Shifting phase can be repeated and it should read the same values. This repetition is used

to improve the reliability of successful reading in a strong EMI environment.

Every register is packed into 4-bytes where the most significant nibble (4 bits) is reserved for

parity code and the rest of 28 bits are used for data. This means that every register is

protected by its own parity bit.

As shown in Figure 6, the first read out byte of data record is Least Significant Byte (LSB) of

data value and the fourth is Most Significant Byte (MSB) of data value, then it is necessary

to re-order the four bytes after reading.

Normally, each byte is read out as most significant bit (MSB) first. But this can be changed

by setting the MSBF configuration bit. If this is done, each byte is read out as least

significant bit (LSB) first.

Figure 6.

STPMxx data registers

7

0

7

0

7

0

7

0

7

0

7

0

15

8

15

8

23

16

23

16

00

24

24

8 bit SPI reading order

32 bits register assembling

msb

lsb

7

0

7

0

7

0

7

0

parity nibble

msb

lsb

parity nibble

28 bit data