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AN3157 数据表(PDF) 7 Page - STMicroelectronics

部件名 AN3157
功能描述  STEVAL-IPE010V1 poly-phase demonstration kit
PDF  26 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN3157 数据表(HTML) 7 Page - STMicroelectronics

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AN3157
Circuit description
Doc ID 17105 Rev 1
7/26
2.2.4
Crosstalk cancellation network
The voltage front-end handles voltages of considerable amplitude, which makes it a
potential source of noise. Disturbances are readily emitted into current measurement
circuitry where they interfere with the actual signal to be measured. Typically, this produces
a non-linear error at small signal amplitudes and non-unity power factors. At unity power
factors, voltage and current signals are in phase and crosstalk between voltage and current
channels merely appears as a gain error, which can be calibrated. When voltage and
current are not in phase, crosstalk has a non-linear effect on the measurements, which
cannot be calibrated.
Crosstalk is minimized through good PCB planning and the proper use of filter components
in the crosstalk network. Recommended filter components are shown in Figure 4. The
network subtracts a signal proportional to the voltage input from the current input. This
prevents crosstalk.
Figure 4.
Daughterboard circuit schematic
1
3
4
5
2
VCC
VCC
VCC
VCC
CLK
CLK
NCLK
NCLK
NCLK
CLK
DAR
R18
0
C13 100n
U1
stpms1
1
2
3
4
9
10
11
12
17
18
vdd_reg
gnd_reg
vdd_ac
gnd_ac
vdd_av
vdd_d
ms0
ms1
e1
e2
J1
Card_Edge_10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C5
1u
C14
1u
VREG
170u
CLK
R7 1K 1%
R16
0
SH1
170u
JP1
1
2
3
4
5
6
7
8
C6
1u
JP2
1
2
3
4
5
6
7
8
TR1
E4622_X503
2
3
C7
5n
C12 100n
R14
10
R8 1K 1%
R6
3.4 1%
C8
5n
DAR
R15
0
D1
C3 22n
R1
82
VCC
C11
1u
N
R4 150k
R11
100 1%
R10
2.2M 1%
R2 150k
GND
R3 150k
D2
L1
220u
VCC
C2 1n
R5
475 1%
R17
10
R9
42.2k 1%
C1 470n
R13 150k
V1
460V
1
2
F
1
3
4
5
2
VCC
VCC
VCC
VCC
CLK
CLK
NCLK
NCLK
NCLK
CLK
DAR
R18
0
C13 100n
U1
stpms1
1
2
3
4
9
10
11
12
17
18
vdd_reg
gnd_reg
vdd_ac
gnd_ac
vdd_av
vdd_d
ms0
ms1
e1
e2
J1
Card_Edge_10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C5
1u
C14
1u
VREG
170u
CLK
R7 1K 1%
R16
0
SH1
170u
JP1
1
2
3
4
5
6
7
8
C6
1u
JP2
1
2
3
4
5
6
7
8
TR1
E4622_X503
2
3
C7
5n
C12 100n
R14
10
R8 1K 1%
R6
3.4 1%
C8
5n
DAR
R15
0
D1
C3 22n
R1
82
VCC
C11
1u
N
R4 150k
R11
100 1%
R10
2.2M 1%
R2 150k
GND
R3 150k
D2
L1
220u
VCC
C2 1n
R5
475 1%
R17
10
R9
42.2k 1%
C1 470n
R13 150k
V1
460V
1
2
F



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