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AN3383 数据表(PDF) 3 Page - STMicroelectronics

部件名 AN3383
功能描述  The purpose of this application note is to describe:
PDF  29 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

AN3383 数据表(HTML) 3 Page - STMicroelectronics

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AN3383
List of figures
Doc ID 018691 Rev 1
3/29
List of figures
Figure 1.
STA350BW 2.0-channel demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2.
Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3.
Block diagram of test connections with equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4.
Top view of PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5.
Bottom view of PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6.
Efficiency (2 channels, BTL configuration), VCC = 26 V, RL = 6 ohm . . . . . . . . . . . . . . . . . . 9
Figure 7.
Efficiency (2 channels, BTL configuration), VCC = 26 V, RL = 8 ohm . . . . . . . . . . . . . . . . . 10
Figure 8.
Output power vs. supply voltage, RL = 6 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9.
Output power vs. supply voltage, RL = 8 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.
Frequency response, VCC = 24 V, RL = 6 ohm, 0 dB (Pout = 1 W) . . . . . . . . . . . . . . . . . . 11
Figure 11.
Crosstalk, VCC = 24 V, RL = 6 ohm, 0 dB (Pout = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12.
SNR, VCC = 24 V, RL = 6 ohm, 0 dB (Pout = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13.
THD vs. frequency, VCC = 24 V, RL = 6 ohm, Pout = 1 W . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.
FFT (0 dBFS), VCC = 24 V, RL = 6 ohm, 0 dBFS (Pout = 1 W) . . . . . . . . . . . . . . . . . . . . . 13
Figure 15.
FFT (-60 dBFS), VCC = 24 V, RL = 6 ohm, 0 dBFS (Pout = 1 W) . . . . . . . . . . . . . . . . . . . . 13
Figure 16.
THD vs. output power, VCC = 24 V, RL = 6 ohm, f = 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17.
Output power = 2 x 5 W, VCC = 26 V, load = 6 ohm, frequency = 1 kHz . . . . . . . . . . . . . . 14
Figure 18.
Output power = 2 x 10 W, VCC = 26 V, load = 6 ohm, frequency = 1 kHz . . . . . . . . . . . . . 14
Figure 19.
Output power = 2 x 15 W, VCC = 26 V, load = 6 ohm, frequency = 1 kHz . . . . . . . . . . . . . 15
Figure 20.
Output power = 2 x 38 W, VCC = 26 V, load = 8 ohm, frequency = 1 kHz . . . . . . . . . . . . . 15
Figure 21.
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22.
Power dissipated over the series resistance [P = C*f*(2*V)2]. . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23.
Power dissipated over the series resistance [P = C*f*2(V2)] . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24.
Damping network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25.
Main filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26.
Recommended power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27.
Snubber network soldered as close as possible to the related IC pin . . . . . . . . . . . . . . . . 19
Figure 28.
Electrolytic capacitor used first to separate the VCC branches . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29.
Path between VCC and ground pin minimized in order to avoid inductive paths . . . . . . . . 20
Figure 30.
Large ground planes on the top and bottom sides of the PCB . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31.
PLL filter soldered as close as possible to the FILT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 32.
Symmetrical paths created for output stage (for differential applications) . . . . . . . . . . . . . 22
Figure 33.
Coils separated in order to avoid crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 34.
VCC filter for high frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 35.
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 36.
Snubber filter for spike high frequency in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 37.
Correct common-mode and differential snubber placement . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 38.
Correct output routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 39.
Comparison of output routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 40.
Thermal layout with large ground (1/3 for top and bottom layers) . . . . . . . . . . . . . . . . . . . 26
Figure 41.
Thermal layout with large ground (2/3 for thermal and soldering holes). . . . . . . . . . . . . . . 26
Figure 42.
Comparison of thermal layout (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 43.
Comparison of thermal layout (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27



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