AN4092 datasheet(21/38 Pages) STMICROELECTRONICS

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AN4092

FMPLL and crystal oscillator

Doc ID 023080 Rev 2

21/38

2.1.2

Recommended crystals

The following quartzes have been characterized (reports are available on demand):

●

NX8045GB 4MHz

●

NX5032GA 8MHz

●

NX3225GA 16MHz

●

NX5032GA 40MHz (SPC564A only)

2.2

Crystal or external reference

The configuration pin PLLREF configures the FMPLL clock reference at reset:

●

Asserted - Indicates that the reference clock comes from the crystal oscillator

●

Negated - Indicates that the reference clock comes from the external clock generator.

In this case the external clock source must be connected to the EXTAL pin while XTAL

must be grounded.

Assertion or negation of the PLLREF(m) must be done at the beginning of the reset cycle

and kept stable for the whole reset duration.

Note:

PLLCFG1 (SPC564Axx BGA324 only) has no PLL configuration functionality anymore. The

name has been kept for legacy reasons.

2.3

Bypass mode or normal mode

In the bypass mode the FMPLL is completely bypassed and the system clock is driven

either from either the crystal oscillator or by an external clock generator connected to the

EXTAL pin. Bypass mode is the default mode at reset.

In the normal mode the FMPLL receives an input clock frequency from either the crystal

oscillator or by an external clock generator and multiplies the frequency to create the

FMPLL output clock.

2.4

Ramp up

As already mentioned, the default system clock after reset is derived from the oscillator.

During ramp-up, it is not desirable to set the FMPLL to jump directly to full operating

frequency. The frequency can be stepped, with delays to allow the power supply to settle.

For example, the target operating frequency of 150MHz (SPC564Axx only) can be reached

in three steps: first to 40MHz, then 80MHz and finally 150MHz.

m. Refer to the Chapter 3: Configuration pins and unused IOs for more details.

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