DocID024130 Rev 2

5/22

AN4231

Low Power Modes overview

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Low Power Modes overview

Many automotive applications need to optimize power consumption in order to preserve the

battery lifetime in all electronic components and minimize electromagnetic emissions.

For this reason, microcontrollers of SPC564Bxx and SPC56ECxx family have the possibility

to remain in particular states called “Low Power Modes” when the primary target is to

minimize the power consumption.

The Low Power Modes in the SPC564Bxx and SPC56ECxx family devices are:



HALT mode



STOP mode



STANDBY mode

The HALT mode is intended as a first level low power mode, in which the platform is stopped

but system clock remains the same as in running mode. This is a reduced-activity low-power

mode during which the clock to the core is disabled. It is configured to switch off analog

peripherals like PLL, Flash, main regulator etc. for efficient power management at the cost

of higher wakeup latency.

The STOP mode is intended as an advanced low power mode, during which the clock of the

platform is disabled. It is possible to switch off most of the peripheral oscillator at the cost of

higher wakeup latency.

The STANDBY mode is a reduced leakage low power mode in which only the power domain

0 (always on) is connected and power supply is cut off from most of the device. Wakeup

from this mode takes a relatively long time and content is lost or must be restored from

backup.

Those modes and their relative power domains are controlled by the Power Control Unit

(MC_PCU) which allows switching through four different power domains.

When a power domain is disconnected from the supply, its power consumption is reduced to

zero and the status information of the same power domain is lost.