DocID025908 Rev 1

13/16

AN4439

Generating a small offset to overcome input resistor tolerance and CSO lower limits

15

These voltages are worst case given the external and internal resistor tolerances. There is a

small overlap that drops below the worst case 0.2 V CSO minimum voltage. The worst case

difference is at the gain of 30 with a 0.012 V error. This translates to a very small sense

current. If this is an issue the next 1% resistor value lower will improve this to above the 0.2

V threshold.

4.1

Bench evaluation

To verify that the additional resistors did not somehow adversely affect the transfer function

of the CSO circuit a bench evaluation was performed. The two resistors were inserted into a

test board as shown in Figure 19 below and the CSI+ pin was driven with a finely adjustable

power supply.

Figure 9. Inserted bias resistors for testing

Table 3. DC offset voltages with given resistor values

CSO DC offset

Gain

Resistor

Min

Typ

Max

20

215

0.202 V

0.304 V

0.416 V

30

143

0.188 V

0.292 V

0.407 V

70

60.4

0.196 V

0.304 V

0.424 V

100

42.2

0.193 V

0.304 V

0.426 V