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PM0014

ST10-DSP features

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ST10-DSP features

ST10 is a combined CPU and DSP.

As a CPU, it is a powerful real time oriented 16-bit CPU.

As a DSP, it is a single MAC 16 by 16-bit multiplier with a 40-bit accumulator.

1.1

Harvard architecture

ST10-DSP has an Harvard architecture to allow on every instruction cycle:

●

1 opcode fetch,

●

2 operand reads,

●

1 optional operand write.

1.2

Multiply and accumulate

ST10 supports different multiply and accumulate instructions with different addressing

modes.

With the CoMAC [Rx+], [Ry+], in a single instruction cycle, ST10 is able to:

●

To fetch 2 operands addressed by Rx and Ry,

●

To update 2 pointers (increment, decrement, add an index)

CoMacM is similar to CoMac except that ST10 also moves 1 operand to the bottom of the

table (useful in data acquisition routines).

1.3

Minimum and maximum

ST10 has 2 instructions for minimum and maximum detection (CoMin and CoMax).

Combined with auto-incrementation, those instructions allow ST10 to scan a table of

samples and detect either the minimum or the maximum in one instruction cycle per sample.

1.4

Instruction repeat unit

Each instruction can be repeated either an immediate number of times or a variable number

of times.

Repeat sequences can be interrupted.

This allows ST10-DSP to compute a FIR (16 by 16; real) at a rate of 1 TAP per instruction

cycle.

1.5

Barrel shifter

ST10-DSP has a barrel shifter connected to the accumulator: any result or value loaded into

the accumulator can be shifted. The shift value must be between 0 and 8 (included).

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