RM0345 datasheet(26/38 Pages) STMICROELECTRONICS

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Calibration software compatibility and configuration

RM0345

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Doc ID 024080 Rev 3

The EBI Option Registers are used to define the address mask and other attributes for the

corresponding chip select.The SCY field of the EBI_CAL_BOx register is detailed in the

Table 15.

Valid bit

The user writes this bit to indicate that the contents of

this Base Register and Option Register pair are valid.

The appropriate CS signal does not assert unless the

corresponding V-bit is set.

0b1

1: This bank is valid

0: This bank is not valid

Table 15.

EBI_CAL_BOx register setting

bit

field

Name

Description

value

0-16

Address Mask

This field allows masking of any corresponding bits in the

associated Base Register.

Masking the address independently allows external

devices of different size address ranges to be used. Any

clear bit masks the corresponding address bit. Any set

bit causes the corresponding address bit to be used in

comparison with the address pins.

Address mask bits can be set or cleared in any order in

the field, allowing a resource to reside in more than one

area of the address map. This field can be read or

written at any time.

24-27

SCY

Cycle length in clocks

This field represents the number of wait states (external

cycles) inserted after the address phase in the single

transfer case, or in the first beat of a burst, when the

memory controller handles the external memory access.

Values range from 0 to 15 and its depends on the RAM

connected on top board.

This is the main parameter for determining the length of

the cycle. These bits are ignored when SETA=1.

The total cycle length for the first beat (including the TS

cycle) = (2+SCY) external clock cycles.

29-30

BSCY

Burst beats length in

clocks

This field determines the number of wait states (external

cycles) inserted in all burst beats except the first, when

the memory controller starts handling the external

memory access and thus is using SCY[0:3] to determine

the length of the first beat.

These bits are ignored when SETA=1.

The total memory access length for each beat is (1 +

BSCY) external clock cycles.

The total cycle length (including the TS cycle) = (2+SCY)

+ (#beats(h)-1) * (BSCY+1).

Table 14.

EBI_CAL_BRx register setting

bit

field

Name

Description

value

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