Peripheral

set max clock

set 1

set 2

set 3

48MHz

48MHz

48MHz

64MHz

64MHz

64MHz

64MHz

64MHz

64MHz

32MHz

64MHz

64MHz

Supply

The Vdd_BV pin also supports an external ballast resistor on the SPC560B64 and SPC560D40

SPC56EC74 requires an external NPN transistor

Power

Domains

PD0 (always on) 16kB RAM

8kB RAM

or 32kB RAM

8kB RAM

or 32kB RAM

8kB RAM

or 32kB RAM,

or 96kB RAM

All device

family

members

have the two

power

domains, with

the user

option to

disable the

main power

domain.

PD1 (main)

Core + peripherals

Remaining RAM + Core

+ peripherals

Remaining RAM + Core +

peripherals

Remaining RAM + Core +

peripherals

MC_RGM

(Reset

Generation

Module)

LVD12 (PD0)

LVD12 (PD1)

LVD27

SWT

POR

LVD45

JTAG

Core Z0

Core Z4

Software

Checkstop

FMPLL

FXOSC fail

CMU

Flash error

External reset

MBIST

Destructive

Destructive

Destructive

Destructive

Destructive

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Destructive

Destructive

Destructive

Destructive

Destructive

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Destructive

Destructive

Destructive

Destructive

Destructive

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Destructive

Destructive

Destructive

Destructive

Destructive

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Functional

Table 1. Overview of differences per module (continued)

Module

name

Sub-modules

SPC560D40

module

SPC560B50

module

SPC560B64

module

SPC56EC74

module

Comment