TN0436

Differences cut1 and cut2

Doc ID 18327 Rev 2

5/10

e5301PS

RGM

MC_RGM: SAFE mode exit may be possible even though

condition causing the SAFE mode request has not been cleared.

e6041PS

ME

MC_ME: peripherals in unknown state after SAFE mode exit.

e6440PS

MC

SWT interrupt does not cause STOP0 mode exit.

e6699PS

CGM

MC_CGM: short glitch may occur on output clock.

e7583 PS

RGM

MC_RGM: RGM_FES content incorrect after startup LBIST

execution.

e8291PS

CGM

System clock source change may cause a "CMU0 system clock

frequency too high or too low event".

e9367PS

eTimer

eTimer: configuring an eTimer counter channel in GATED-

COUNT mode or in SIGNED-COUNT mode it may cause a

possible incorrect counting of 1 tick.

e9414PS

eTimer

Possible false DMA requests from eTimer.

e6886PS

NPC

MCKO clock gating not implemented.

e9376 PS

PWM

FlexPWM: configuring the count value to set PWMA/PWMB first

low and then high in the same cycle the output signals are low.

e6309PS

SSCM

Debugging functionality could be lost when unsecuring a secured

device.

e6500PS

ADC

VREFP and VDD_HV_ADC power up sequencing constraint.

e5485PS

ADC

ADC: ADC_DMAE[DCLR] should not be used.

e9154 PS

ADC

ADC: abort request during last sampling cycle corrupts the data

register of next channel conversion.

e1685PS

FMPLL

FMPLL: FMPLL_CR[UNLOCK_ONCE] wrongly set.

e7220PS

SWG

SWG: SGEN_CTRL.NRO bit is reserved *).

e5816PS

SWG

SWG: Sinewave generator (SWG) is active during self-test

execution.

e26553IPG

e200z4

e200z4: mtlr followed by se_rfi/se_rfci/se_rfdi/se_rfmci can give

unexpected results.

e8099 PS

DMA

Limiations for DMA access to LINFlex.

e9471 PS

IPBUS

CAN Register/Message Buffer Access can reset or block the

device if certain clock divider ratios (PeriN: System Clock) are

selected.

e7752PS

Platform

ICache commands ICBTLS and ICBLC do not work as specified.

Table 2.

Errata for cut1 and the fixes for cut2 (continued)

Errata number

Module

Description