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AN1301

APPLICATION NOTE

November 2003

1.0 GENERAL DESCRIPTION

The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for

10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media

Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical me-

dia interface for 100BASE-TX and 10BASE-T. The twisted pair interface directly drives a 10/100 twisted pair

connection. STE100P is an excellent device perfectly suited for hub, switch, router and other embedded Ether-

net applications.

The system diagram is as shown below:

Figure 1. System Diagram of the STE100P Application

2.0 FEATURES

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Integrates the whole physical layer functions of the 100BASE-TX and 10BASE-T

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3.3V low power operation

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The hardware control pins set the initial state of the STE100P at power-up

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Designed with a power down feature, which can save the power consumption significantly

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Can operate for either full duplex or half duplex network applications.

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MII interface

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Provides auto-negotiation, parallel detection or manual control for mode setting

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Provides MLT-3 transceiver with DC restoration for Base-line wander compensation

B oot R O M

25 M H z

C r ysta l

RJ -4 5

ST E1 0 0 P

STEP HY1

Se r ia l

EEPR O M

LE D s

M A C

D ev ic e

STE100P - SINGLE PORT FAST ETHERNET TRANSCEIVER