AN1318 - APPLICATION NOTE

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Table 3: Electrical characteristics comparison of the differential logic families

5. INTERFACING LVPECL TO LVDS.

To accomplish LVPECL to LVDS interfacing the proposal scheme uses the Thevenin Equation to fix the

static level of the LVDS input. The LVPECL differential output swing will surely go over the LVDS input

circuitry level.

Figure 5: LVPECL to LVDS Interfacing Diagram

This schematic is supplied by 3.3V, the termination of the transmission line Z can be calculated with the

Thevenin equation.

- The characteristic line impedance:

- The DC condition for point A is VCC -2V

Symbol

Parameter

LVDS

LVPECL

PECL

ECL

VCC

3.3V

3.3V

5.0V

GND

VEE

GND

GND

GND

-5.2V, -4.5V or -3.3V

VOH

Minimum Output High Level

1.250V

2.275V

3.975V

-1.030V

VOH

Typical Output High Level

1.375V

2.345V

4.045V

-0.955V

VOH

Maximum Output High Level

1.600V

2.420V

4.120V

-0.880V

VOL

Minimum Output Low Level

0.900V

1.490V

3.190V

-1.810V

VOL

Typical Output Low Level

1.025V

1.595V

3.295V

-1.705V

VOL

Maximum Output High Level

1.250V

1.680V

3.380V

-1.620V

VCC = 3.3V

LVPECL

Z

Z

R1

R1

R2

R2

R3

R3

VCC = 3.3V

LVDS

3.3V

A

A

B

B

ZR1

R2

R3

+

()

||

=