AN2269 datasheet(21/25 Pages) STMICROELECTRONICS

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AN2269 - Application Note

ST8024 Application Hardware Guidelines

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4.3

Smart Card Connections

In typical applications, a 100nF filter capacitor (C3) is connected to the VCC output towards

GND/CGND, near the ST8024 pins. A second 100nF capacitor (C8) is connected between

the card socket pins C1 (VCC) and C5 (CGND), near the card slot (see Figure 19). In order

to reduce noise and avoid coupling effects, the wire length between the ST8024 and card

should be as short as possible.

Another recommendation is to keep the CLK track far away from the other signal tracks to

limit coupling with the transceiver lines. Further decoupling is gained if the clock track is

shielded by a GND/CGND plane or track on the PCB.

Keeping the PGND and GND/CGND planes as large as possible improves power supply

noise rejection. With this in mind, the board design should connect these planes with a large

number of vias between the top and bottom board layers (3-4 vias per cm2).

The VCC spikes are much lower than 350mVPP, even when a pulsed load of up to 80mA is

applied with VCC = 5V, or up to 65mA with VCC = 3V, as specified by the NDS requirements.

Figure 20 on page 22 shows a typical VCC output waveform where an 80mA pulsed load

applied and the measured ripple is lower than 160mVPP.

Figure 19.

ST8024 Application PCB Smart Card Connections

AN2269 数据表(PDF) 21 Page - STMicroelectronics