AN3392 datasheet(23/57 Pages) STMICROELECTRONICS

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AN3392

Voltage regulation

Doc ID 018749 Rev 1

23/57

The SPV1020 implements an internal control guaranteeing the current balance between the

four branches, monitoring the current flowing on each branch with a maximum variation of

350 mA.

7.4

SPI serial peripheral interface

The SPV1020 implements a 4-pin compatible SPI interface. The SPI allows full duplex,

synchronous, serial communication between a host controller (the master) and the

SPV1020 peripheral device (the slave). The SPV1020 provides the following 4 pins:

●

XCS (or SS)

●

SPI_CLOCK (or SCLK)

●

SPI_DATA_IN (or MOSI)

●

SPI_DATA_OUT (or MISO).

Figure 21.

SPI interface: master/slaves connection example

The SPI master selects one of the slaves, provides the synchronizing clock and starts the

communication. The idle state of the serial clock for the SPV1020 is high, while data pins

are driven on the falling edges of the serial clock and are sampled on its rising edges (SPI

control bits CPOL = 1, and CPHA = 1). The bit order of each byte is MSB first.

When the master initiates a transmission, a data byte is shifted out through the MOSI pin to

the slave, while another data byte is shifted out through the MISO pin to the master; the

master controls the serial clock on the SCLK pin. The SS (active low) pin must be driven low

by the master during each transmission.

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