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AN4540 数据表(PDF) 3 Page - STMicroelectronics |
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AN4540 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 11 page ![]() DocID026512 Rev 1 3/11 AN4540 MHL link 11 1 MHL link This link is based on a single high-speed differential pair (TMDS). It carries out a CBUS, a single wire control bus replacing DDC bus, and VBUS power supply (Figure 1). Figure 1. MHL block diagram MHL 2.0 maximum data rate is 3 Gbps and goes up to 6 Gbps in the latest version (3.0). The clock is embedded in common mode up to 75 MHz for 1080 p/ 60 Hz video resolution. The connector is µUSB standard (Figure 2). Figure 2. MHL connector Figure 3 describes signals found on the link. |
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