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AN458 APPLICATION NOTE

Figure 11. Powerdip 12+3+3 Pin Connection

POWER SUPPLY

The device has two separate pins dedicated for the supply source. Pin.1 is for the Signal (Vcc) and Pin.3 for the

Power (Vss) source; normally these two pins are connected together (see the typical application circuit Fig. 18).

The L4963 is provided with an internal stabilized power supply that feeds the precise internal voltage reference

5.1V (±2%) and the internal analog blocks.

UNDER VOLTAGE LOCK OUT (UVLO)

The UVLO circuit ensures that Vcc is adequate to make the L4963 fully operational before enabling the output

power stage. The UVLO turn-on and turn-off thresholds are internally fixed at 8.4V and 7.9V respectively.

This function acts also on the Power Fail and Reset Circuits; their output voltages pin.8 and pin.10 respectively,

remain low state until the turn-on threshold is reached.

OSCILLATOR

The oscillator circuit behaves in a completely different way compared to the usual Step-Down regulator operat-

ing at fixed frequency and variable duty cycle. In fact, usually, the oscillator generates a fixed frequency saw-

tooth waveform that is compared with the Error Amplifier output voltage, generating the PWM signal to be sent

to the power output stage.

In the L4963, the oscillator function is quite different. In the following we will describe briefly its operation refer-

ring to the simplified internal schematic shown in fig.12. It is composed of a comparator (with inputs compatible

to ground) with an hysteresis whose thresholds are 1V and 4.1V respectively.

The oscillator uses an external resistor RT on pin.18 to establish the charging and discharging current of the

internal timing capacitor CT = 50pF, fixing in this way the maximum switching frequency:

It is also possible to increase the internal timing capacitor value, connecting an external capacitor between

pin.17 and ground. The oscillator circuit, as we have seen in the "CIRCUIT OPERATION" paragraph, sends a

set pulse to the latch that enables the power stage. This set pulses train is at fixed frequency imposed by the

f

()

0.033

Rt K

Ω

()

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