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AN487 APPLICATION NOTE

When the comparator senses an overcurrent, the

flip-flop is set and an internal inhibit signal is gen-

erated. The flip-flop remains set until next reset

clock pulse coming from the internal 40 KHz oscil-

lator. After the reset pulse the regulation loop

takes the control of the system and the output cur-

rent begins to increase to the load value at the

switching frequency of the master clock.

If the

overload condition is still present the protection cy-

cle repeats. This mixed, pulse by pulse, lowering

frequency current protection method, assures a

constant current output when the system is in

overload or short circuit and allows to implement a

reliable current limitation even at high switching

frequency (500 KHz) reducing the problems of sig-

nal delay through the protection stage. Fig.22

shows behavior of the inductance current when

the system is in overload.

Figure 22. Overload inductance current.

The internal 40 KHz oscillator is synchronized with

the master clock. When the system works with the

master clock at a lower frequency of the internal

clock, than the internal clock tracks the master fre-

quency. This assures that the frequency does not

increas during overload.

POWER FAIL-RESET CIRCUIT

The L4970A include a voltage sensing circuit that

may be used to generate a power on power off re-

set signal for a microprocessor system. The circuit

senses the input supply voltage and the output

generated voltage and will generate the required

reset signal only when both the sensed voltages

have reached the required value for correct sys-

tem operation. The Reset signal is generated after

a delay time programmable by an external capac-

itor on the delay pin. Fig. 23 shows the circuit im-

plementation of Reset circuit. The supply voltage

is sensed on an external pin, for programmability

of the threshold, by a first comparator. The second

comparator has the reference threshold set at

slightly less the ref. voltage for the regulation cir-

cuit and the other input connected internally at the

feedback point on the error amplifier. This allows

to sense the output regulated voltage. When both

the supply voltage and the regulated voltage are in

the correct range, transistor Q1 turns off and al-

lows the current generator to charge the delay ca-

pacitor. When the capacitor voltage reaches 5V

the output Reset signal is generated. A latch as-

sures that if a spike is present on the sensed volt-

age the delay capacitor discharges completely

before initialization of a new Reset cycle. The out-

put gate assures immediate take of reset signal

without waiting for complete discharge of delay ca-

pacitor. Reset output is an open collector transis-

tor capable of sinking 20mA at 200mV volt-

age.Fig. 24 shows reset waveforms.

Figure 23.