AN1344

Layout considerations

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Layout considerations

Some simple rules to improve the performance and minimize noise should be followed:

1.

Minimize power loops. Switched power current paths inner loop area must be as small

as possible. This can be achieved by careful layout of the printed circuit board. This

avoids radiated and conducted EMI noise, and improves efficiency by eliminating

parasitic inductance, thus reducing or eliminating the need for snubbers and EMI

filtering.

2.

Use separate tracks for low level signal and power traces carrying fast switching pulses.

This can be seen on the VIPer100A-E pin 4. Ground is split between power and signal

traces on the printed circuit lay out. When signal paths share the same trace as a

power path, instabilities may result. The compensation components, C7, R6, and C9

are on a separate trace connected directly to the source of the device.

4

Burst mode

When the output current is too low, the minimum on time, fixed by the internal blanking time,

is too high to control the output voltage. In this case the burst mode operation takes over

automatically. The VIPer100A-E switch stays off when the voltage on the compensation pin

minimum output current is at 40 mA.

Figure 6.

Good burst mode

As can be seen, there is a burst of pulses followed by a pause of 600 ms. This repetitive

burst reduces power consumption while maintaining a negligible ripple on the output. The

out. The under voltage lock out can be reached by further reducing the output current. As

below the under voltage lock out of 8 V, another type of burst mode appears which is

drawbacks, but the output voltage is still under control.