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AN1376 数据表(PDF) 5 Page - STMicroelectronics |
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AN1376 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 35 page ![]() 5/35 AN1376 APPLICATION NOTE Figure 2. Vds & Id @ Full Load The pictures above show the drain voltage and current at the nominal input mains voltage dur- ing normal operation at full load. The Envelope acquisition of the scope provides for the pos- sibility to see the modulation of the two waveforms due to the input voltage ripple. Figure 3. Vds & Id @ Full Load (Vin = 265 Vrms - 50 Hz) Figure 4. Vin = 265 Vrms - 50 Hz, @FULL LOAD: DIODE PIV Vin = 115 Vrms - 50 Hz Vin = 220 Vrms - 50 Hz CH1: DRAIN VOLTAGE; CH2: RAIN CURRENT - VR.SENSE (R6) CH1: DRAIN VOLTAGE; CH2: RAIN CURRENT - VR.SENSE (R6) This picture gives the measurement of the drain peak voltage at full load and maximum input mains voltage. The voltage peak, which is 548V, assures a reliable operation of the PowerMOS with a good margin against the maximum BVDSS. CH3: +35V DIODE: ANODE VOLTAGE; CH4: +12V DIODE: ANODE VOLTAGE CH3: +7V DIODE: ANODE VOLTAGE; CH4: +3V3 DIODE: ANODE VOLTAGE |
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