AN2836 datasheet(13/57 Pages) STMICROELECTRONICS

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AN2836

Designing an application with L6225, L6226, L6227

Doc ID 15084 Rev 1

13/57

For example, if a maximum ripple of 500 mV is allowed and IOUT = 1 A, the capacitor ESR

should be lower than:

Equation 6

Equation 7

Actually, current sunk by the VSA and VSB pins of the device is subject to higher peaks due

to the reverse recovery charge of the internal freewheeling diodes. The duration of these

peaks is, though, very short, and can be filtered using a small value (100÷200 nF), good

quality ceramic capacitors, connected as close as possible to the VSA, VSB and GND pins of

the IC. The bulk capacitor will be chosen with maximum operating voltage 25% greater than

the maximum supply voltage, considering also power supply tolerances. For example, with a

48 V nominal power supply, with 5% tolerance, maximum voltage is 50.4 V, then operating

voltage for the capacitor should be at least 63 V.

4.4

Layout considerations

Working with devices that combine high power switches and control logic in the same IC,

special attention has to be paid to the PCB layout. In extreme cases, power DMOS

commutation can induce noise that could cause improper operation in the logic section of

the device. Noise can be radiated by high dV/dt nodes or high dI/dt paths, or conducted

through GND or supply connections. Logic connections, especially high-impedance nodes

(actually all logic inputs, see further), must be kept far from switching nodes and paths. With

the L6225, L6226, L6227, in particular, external components for the charge pump circuitry

should be connected together through short paths, since these components are subject to

voltage and current switching at relatively high frequency (600 kHz). The primary means to

minimize conducted noise is to have a good GND layout (see Figure 7).

Figure 7.

Typical application and layout suggestions

ESR

0.5V

------------

500m

In slow decay

In fast decay

ESR

---

0.5V

------------

⋅

250m

AM01627v1

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