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AN2872 数据表(PDF) 13 Page - STMicroelectronics |
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AN2872 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 23 page ![]() AN2872 Experimental results Doc ID 15305 Rev 1 13/23 4 Experimental results 4.1 Load regulation and output voltage ripple The 12 V output is affected by the load due to the effects described in Chapter 3.1.2 and 3.2. The real load regulation of the 12 V output (linear regulator U2 is not assembled) for different input voltages is visible in Figure 6. Figure 6. 12 V output load regulation for different output loads and input voltage levels (linear regulator U2 not assembled) The flatness of the load characteristic can be influenced mainly at light load by setting a fixed load (a resistor instead of Zener diode D2) or assembling a linear regulator to represent light load. The behavior of the load characteristic can be influenced by the value of the auxiliary capacitor C8 and total value of resistance of R3 and R4. The output voltage ripple is very low and presents a good opportunity to use smaller capacitors with higher ESR and lower capacitance. The data measured with the demonstration board are shown in Figure 7. It is possible to see the higher 100 Hz ripple at 90 VAC on the input. This ripple can be avoided by increasing the capacitance of the input capacitors. 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 -20 0 20 40 60 80 100 120 140 160 IOUT (mA) VOUT (V) 500 V AC 400 V AC 230 V AC 120 V AC 90 V AC AM00362 |
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