µPD17P236

21

Data Sheet U14776EJ1V0DS00

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-level input voltage

Other than CLK

V

CLK

V

Low-level input voltage

Other than CLK

0

V

CLK

0

0.4

V

Input leakage current

10

µA

High-level output voltage

V

Low-level output voltage

0.4

V

30

mA

30

mA

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2

µs

2

µs

2

µs

2

µs

2

µs

↑→ data output float delay time

0

130

ns

2

µs

2

µs

Initial program pulse width

0.95

1.0

1.05

ms

Additional program pulse width

0.95

21.0

ms

2

µs

↓→ data output delay time

1

µs

≥ 50

µs2

µs

2

µs

Program counter reset time

10

µs

CLK input high-, low-level width

0.125

µs

CLK input frequency

4.19

MHz

Initial mode set time

2

µs

2

µs

2

µs

When program memory is read

2

µs

→ data output delay time

When program memory is read

2

µs

→ data output hold time

When program memory is read

0

130

ns

When program memory is read

2

µs

↓→ data output float delay time

When program memory is read

2

µs

Reset setup time

10

µs

Note

The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks compreise one

cycle. The internal clock is not connected to a pin.