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RH1011 数据表(PDF) 2 Page - Linear Technology

部件名 RH1011
功能描述  Voltage Comparator
PDF  2 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

RH1011 数据表(HTML) 2 Page - Linear Technology

  RH1011_15 Datasheet HTML 1Page - Linear Technology RH1011_15 Datasheet HTML 2Page - Linear Technology  
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DICE SPECIFICATION
RH1011
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LT/LT 0603 REV B • PRINTED IN USA
©LINEAR TECHNOLOGY CORPORATION 2000
Rad Hard die require special handling as compared to standard IC
chips.
Rad Hard die are susceptible to surface damage because there is no
silicon nitride passivation as on standard die. Silicon nitride protects
the die surface from scratches by its hard and dense properties. The
passivation on Rad Hard die is silicon dioxide that is much “softer”
than silicon nitride.
LTC recommends that die handling be performed with extreme care so
as to protect the die surface from scratches. If the need arises to move
the die around from the chip tray, use a Teflon-tipped vacuum wand.
This wand can be made by pushing a small diameter Teflon tubing
onto the tip of a steel-tipped wand. The inside diameter of the Teflon
tip should match the die size for efficient pickup. The tip of the Teflon
should be cut square and flat to ensure good vacuum to die surface.
Ensure the Teflon tip remains clean from debris by inspecting under
stereoscope.
During die attach, care must be exercised to ensure no tweezers touch
the top of the die.
Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on
dice performance and lot qualifications via lot sampling test procedures.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-1011
DICE ELECTRICAL TEST LI ITS V
S = ±15V, VCM = 0V, RS = 0Ω, TJ = 25°C, VGND = V
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
VOS
Input Offset Voltage
(Note 2)
1.5
mV
RS ≤ 50k (Note 3)
2.0
mV
IOS
Input Offset Current
(Note 3)
4nA
IB
Input Bias Current
(Note 2)
50
nA
(Note 3)
65
nA
AVOL
Large-Signal Voltage Gain
VS = ±15V, RL = 1k, –10V ≤ VOUT ≤ 14.5V
200
V/mV
VS = 5V, RL = 500Ω , 0.5V ≤ VOUT ≤ 4.5V
50
V/mV
CMRR
Common Mode Rejection Ratio
90
dB
Input Voltage Range
VS = ±15V
–14.5
13
V
VS = Single 5V
0.5
3
V
VOL
Output Saturation Voltage
VIN
= 5mV, VGND = 0V, ISINK = 8mA
0.4
V
ISINK = 50mA
1.5
V
Output Leakage Current
VIN+ = 5mV, VGND = –15V
10
nA
VOUT = 20V
Positive Supply Current
(Note 4)
4mA
Negative Supply Current
(Note 4)
2.5
mA
Strobe Current
Minimum to Ensure Output Transistor Is Off (Notes 4, 5, 6)
500
µA
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: Output is sinking 1.5mA with VOUT = 0V.
Note 3: These specifications apply for all supply voltages from a single
5V to
±15V, the entire input voltage range and for both high and low
output states. The high state is ISINK ≥ 100µA, VOUT ≥ (V+ – 1V) and
the low state is ISINK ≤ 8mA, VOUT ≤ 0.8V. Therefore, this specification
defines a worst-case error band that includes effects due to common
mode signals, voltage gain and output load.
Note 4: VGND = 0V
Note 5: Do not short the STROBE pad to ground. It should be current
driven at 3mA to 5mA for the shortest strobe time. Currents as low as
500
µA will strobe the RH1011 if speed is not important. External
leakage on the STROBE pin in excess of 0.2
µA when the strobe is “off”
can cause offset voltage shifts.
Note 6: Guaranteed by design, characterization or correlation to other
tested parameters.
Note 7: Please refer to LTC standard product data sheets for all other
applicable information.



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