AN3063

Main characteristics and circuit description

Doc ID 16261 Rev 3

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C13, R27 and R32, connected to pin #5 VFF, complete an internal peak-holding circuit that

derives the information on the RMS mains voltage. The voltage signal at this pin, a DC level

equal to the peak voltage on pin #3 (MULT), is fed to a second input to the multiplier for the

voltage. Additionally, pin #12 RUN is connected to pin# 5 VFF through a resistor divider R27

and R32, providing a voltage threshold for brownout protection (AC mains undervoltage) . A

voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a

considerably lower level. The L6563H restarts as the voltage at the pin rises above 0.88 V.

The divider R3, R6, R11 and R15 provides the L6563H pin #7 (PFC_OK) with the

information regarding the output voltage level. It is required by the L6563H output voltage

monitoring and disables functions used for PFC protection purposes.

If the voltage on pin #7 exceeds 2.5 V, the IC stops switching and restarts as the voltage on

the pin falls below 2.4 V, implementing the so-called dynamic OVP which prevents an

excessive output voltage in case of transients, because of the slow response of the error

amplifier. However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.)

a feedback failure is assumed. In this case the device is latched off. Normal operation can

be resumed only by cycling Vcc, bringing its value lower than 6V before rising up to the turn-

on threshold.

Additionally if the voltage on pin #7 (PFC_OK) is tied below 0.23 V, the L6563H is shut

down. To restart operation of the L6563H the voltage on pin #7 (PFC_OK) has to increase

above 0.27 V. This function can be used as a remote on/off control input.

To allow interfacing of the board with a D2D converter, the connector J3 allows powering the

L6563H with an external Vcc and also manages failure or abnormal conditions via the pins

PWM_LATCH and PWM_STOP. The L6563H can be also disabled or enabled to manage

properly light load or failure by the D2D via the PFC_OK pin #7, available at pin #5 of J3

(ON/OFF) For further details please see

Section 4.7.