AN3064

STC3100 register map

Doc ID 16263 Rev 1

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Table 12.

REG_MODE. address 0 (00h)

Name

Pos.

Type

Power-

up

Description

SEL_EXT_CLK

0

R/W

0

32,768 Hz clock source:

0: auto-detect, 1: external clock

GG_RES

[2,1]

R/W

00

Current/Coulomb counter ADC resolution:

00: 14 bits, 01: 13 bits, 10: 12 bits

GG_CAL

3

R/W

0

0: no effect

1: used to calibrate the AD converters

GG_RUN

4

R/W

0

0: standby mode. Accumulator and counter

registers are frozen, battery monitoring functions

are in standby.

1: operating mode

[7..5]

Unused

Table 13.

REG_CTRL. address 1 (01h)

Name

Pos.

Type

Power-

up

Description

IO0DATA

0

RX

Port IO0 data status:

0 = IO0 input is low, 1 = IO0 input is high

W1

Port IO0 data output drive:

0 = IO0 output is driven low,1 = IO0 output is open

GG_RST

1

W

0

0: no effect

1: resets the charge accumulator and conversion

counter. GG_RST is a self-clearing bit.

GG_EOC

2

R

1

Set at the end of a battery current conversion

cycle. Clears upon reading.

VTM_EOC

3

R

1

Set at the end of a battery voltage or temperature

conversion cycle. Clears upon reading.

PORDET

4

R1

Power-on reset (POR) detection bit:

0 = no POR event occurred

1 = POR event occurred

W0

Soft reset:

0 = releases the soft-reset and clears the POR

detection bit

1 = asserts the soft-reset and sets the POR

detection bit

[7..5]

R/W

Unused