AN3090

Error detection output test circuit

Doc ID16496 Rev 1

13/19

4

Error detection output test circuit

During the error detection time, the internal structure of the device allows a single output

current test. Specifically, the test is performed by comparing the current flowing from the

device marks the output as malfunctioning, and converts the previous data loaded into the

shift register from “1” to “0”. Subsequently, these results are transferred as feedback by the

SDO pin.

Table 2 shows a typical example of the measured error detection threshold for several

For output error detection to function correctly, all the signals must be synchronized with the

falling edge of the CLK signal. This is necessary to avoid any setup\hold time violations.

In some cases, due to application conditions, this cannot be applied (i.e.: data generated by

an MCU). To address this, it is possible to switch all of the other signals by applying a 15 ns

delay after the rising edge of the CLK signal.

Only one error detection reading can be made within the acquisition time window. For this

reason, if two or more readings are required it is necessary the complete the error detection

sequence, then repeat each step again.

Table 2.

Error threshold test results

Measured error threshold (mA)

3.3

1

0.359

2

0.841

31.36

52.10

10

4.80

20

10.2

40

19.68

5.0

1

0.355

2

0.831

31.21

52.40

10

5.00

20

9.90

40

19.55