AN3352

Layout guidelines

Doc ID 018526 Rev 3

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3.2

PCB thermal management

The LNBH24L power dissipation inside the IC is mainly due to the DC-DC integrated

MOSFET power loss plus the linear regulator power dissipation. The total power dissipation

calculated, considering both the DC-DC and linear regulator power loss at the maximum

W. The heat generated due to this power dissipation level requires a suitable heatsink to

keep the junction temperature below the overtemperature protection threshold at the rated

ambient temperature inside the set-top box.

The best thermal and electrical performance can be achieved when an array of copper vias

barrel plating is incorporated in the land pattern at 1.2 mm grid. It is also recommended that

the via diameter should be 0.30 mm to 0.33 mm with 1 oz copper via barrel plating.

If the copper plating does not plug the vias, a solder mask material must be used to cap the

vias with a dimension equal to the via diameter + 0.1 mm minimum. This prevents the solder

from not being well spread through the thermal via and potentially creating a solder void

between the package bottom and the ground plane of the PCB.

Taking into account that the solder mask diameter should be at least 0.1 mm larger than the

via diameter.

However, different layouts are also possible. Basic principles suggest keeping the IC and its

ground exposed pad approximately in the middle of the dissipating area; to provide as many

vias as possible; to design a dissipating area having a shape as square as possible and not

interrupted by other copper traces.