AN3395

Rcg layout considerations

Doc ID 018779 Rev 1

7/11

4

Rcg layout considerations

Figure 3 shows the recommended layout of the PCB for Rcg.

Figure 3.

Rcg recommended layout with the STC3105

In order to obtain the most accurate SOC estimation, follow these recommendations:

1.

Place Rcg as close as possible to the CG pin.

The STC3105 measures the battery current by sensing the voltage between the CG

and GND pin. Between these two pins are two PCB traces and Rcg. Any voltage drop

on the traces will directly add error to the measurement. The shorter the traces are, the

better the accuracy of the measurement obtained.

2.

The STC3105 GND pin should be connected directly to a terminal of Rcg (CG– in

Figure 3), not through the ground plane. This Rcg terminal (CG– in Figure 3) should

be connected to the ground plane on the PCB.

This connection avoids the occurrence of high current through Rcg to the voltage

potential on the STC3105 GND pin. Any ground disturbances will directly affect the

accuracy of the current measurement and therefore the SOC estimation.

3.

If the STC3105 is on a PCB near RF components, special care should be taken to

avoid ground disturbance by the RF interference.

The user can simply connect two high-frequency ceramic capacitors in parallel with

Rcg to minimize the RF effect, if needed. The capacitance should be selected based on

the frequencies which produce the highest RF disturbance. For example,

15 pF (ex. Murata 15 pF, part code: GQM2195C2A150GB01) and 68 pF (ex. Murata

68 pF, part code: GQM1885C1H680GB01) can be selected to avoid the disturbances

from 1.8 GHz and 900 MHz (strongest RF power in a cell phone). This is illustrated in

Figure 4 on page 8.

AM045293v1