AN4345 datasheet(5/28 Pages) STMICROELECTRONICS

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AN4345

Circuit description

The converter schematic is given in Figure 4. The input section includes a resistor R1 for

inrush current limiting, diodes D1 and D2 and a Pi filter (C1, L1, C2) for rectification and

EMC suppression.

The FB pin is the inverting input of the internal transconductance error amplifier and its

reference voltage is VFB_REF = 3.3 V. The output voltage VOUT1 is regulated by the voltage

divider, which is composed of R4 and R5, according to the following formula:

Equation 1

where R5 is split into R5A and R5B to allow a better tuning of the output voltage.

VOUT2 comes from VOUT1 through a linear voltage regulator, the compensation is performed

by the R-C-C network connected between COMP and GND pins.

At power-up, the DRAIN pin supplies the internal HV start-up current generator, which

charges the C3 capacitor up to VDDON (13 V). At this point, the power MOSFET starts

switching, the generator is turned off and the IC is powered by the energy stored in C3.

If the jumper J1 is not selected, the VIPer16LD is self-biased: the C3 capacitor voltage, due

to the system consumption, falls down and when it reaches VDDCS_ON (10.5 V typ.), the

internal HV current generator is turned on, recharging C3 up to VDDON, after that the HV

generator is switched off again. The VIPer16LD is internally supplied without any external

network, which minimizes the number of external components. Moreover this function

allows the designer to generate output voltages below the voltage lockout (5 V for example)

with a simple inductor.

If the jumper J1 is selected, the HV start-up generator is activated at power on only: when

VOUT1 has reached its steady-state value, IC is biased from the output through the diode

D6, allowing the system to reach very low standby-consumption values. This is referred to

“external biasing” and can be obtained only if VOUT1 is high enough to keep the C3 voltage

always above the VDDCS_ON threshold.

The shape of the VDD voltage is depicted in Figure 5 and 6 for self-biasing and external

biasing respectively.

The R6 resistor, if connected, reduces the default current limitation of the device IDLIM by a

certain percentage depending on the resistor value, as reported in the curve ILIM vs. RLIM of

the datasheet. This optimizes the design of the magnetic and power elements.

REF

OUT

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