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AN4505 数据表(PDF) 31 Page - STMicroelectronics |
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AN4505 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 43 page  DocID026441 Rev 1 31/43 AN4505 First-in first-out (FIFO) buffer 43 Figure 16. FIFO_EN connections block diagram 6.2.2 FIFO control register (0x2E) This register is dedicated to FIFO mode selection and watermark configuration. FM[2:0] bits are dedicated to defining the FIFO buffer behavior: 1. FM[2:0] = (0,0,0): Bypass mode 2. FM[2:0] = (0,0,1): FIFO mode 3. FM[2:0] = (0,1,0): Stream mode 4. FM[2:0] = (0,1,1): Stream-to-FIFO mode 5. FM[2:0] = (1,0,0): Bypass-to-Stream mode The trigger used to activate Stream-to-FIFO and Bypass-to-Stream modes is related to the IA bit value of the selected INT1_SRC register and does not depend on the interrupt pin value and polarity. The trigger is generated also if the selected interrupt is not driven to an interrupt pin. The WTM[4:0] bits are intended to define the watermark level; when FIFO content exceeds this value, the WTM bit is set to “1” in the FIFO source register. Table 30. FIFO_CTRL_REG b7 b6 b5 b4 b3 b2 b1 b0 FM2 FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0 |
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