DocID3567 Rev 4

9/17

AN316

Speed

17

4.2

Connection effect

Figure 8. Example of PCB Layout

Figure 8 gives an example of a PCB Layout. On this portion of PCB, an integrated circuit

(IC1) is connected to outside equipment through the connector J1. A cable can be hot

plugged in J1 and then causes ESD on all the lines linked to J1. In this case the pin 2 of IC1

is connected to the pin 2 of the connector J1 and the Transil T1 assumes the protection of

this line.

When a surge occurs on pin 2 of the connector, this is clamped by T1. During the surge, the

remaining voltage at the pin 2 level of IC1 is the potential difference between both points A

and B.

In case of ESD, the rise time of the surge is within 1 ns and we have to take into account the

parasite inductances located between A and T1 (L1) and T1 and B (L2). So the remaining

and the voltage induced by L1 and L2.

In case of Figure 8, the Track length between A and T1 is 10mm and between T1 and B is

5 mm. We can estimate the parasitic inductance of the track at 1 nH/mm, so L1

≈ 10 nH and

L2

≈ 5 nH. The remaining voltage between A and B is equal to:

Equation 4

With

value measured during IEC 61000-4-2 8 kV contact discharge ESD Test.

In this case an extra voltage of 300 V is due to the PCB tracks. Figure 9 gives a solution to

this problem.

V

V

V

V

dt

di

L

L

V

CL

CL

CL

300

10

20

10

)

5

10

(

)

(

9

9

2

1

+

=

+

+

=

+

+

-

-

×

×

×

ns

A

dt

di

/

20

=