D4723GS datasheet(2/16 Pages) NEC

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µPD4723

BLOCK DIAGRAM/PIN CONFIGURATION (Top View)

DIN1

DIN2

DIN3

ROUT1

ROUT2

ROUT3

STBY

VCHA

DOUT1

DOUT2

DOUT3

RIN1

RIN2

RIN3

VDD

C1+

VCC

C1–

C5+

GND

C5–

C4+

GND

C4–

VSS

+10 V

–10 V

Note 4

300

Ω

300

Ω

300

Ω

5.5 k

Ω

5.5 k

Ω

+3.3 V

+5 V

5.5 k

Ω

Note 1. VDD and VSS are output pins stepped up internally. These pins should not be loaded directly.

2. Capacitors C1 to C5 with a breakdown voltage of 20 V or higher are recommended. And it is recommended

to insert the capacitor that is 0.1

µF to 1 µF between VCC and GND.

3. If VCHA is kept low level (in 5 V mode), capacitor C5 is not necessary.

4. The pull-up resistors at driver input are active resistors.

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