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UM1753

STLUX library

CLK_GetITStatus

CLK_IT specifies the CLK

interrupt.

ITStatus is the

current status

for the interrupt.

Checks whether the

specified CLK interrupt has

is enabled or not.

CLK_ClearITPendingBit

CLK_IT specifies the CLK

interrupt.

Clears the CLK's interrupt

pending bits.

CLK_PLLConfig

CLK_PLL_Source specifies the

clock source for the PLL. It can

be HSI or HSE.

CLK_PLL_DIVPRES is the

division factor for PLL selected

clock.

This function sets the clock

source for PLL.

CLK_PLLCmd

NewState can be ENABLE or

DISABLE.

This function enables or

disables PLL.

CLK_CCOConfig

CLK_CCO specifies the clock

source for the CCO. It can be

one of the following sources:

HIS, LSI, HSE, PLL, CPU,

CKM, SMEDx, ADC, EEPROM,

AWU, prescaled PLL.

CLK_CCODIVR is the division

factor n for the CCO clock,

CLKCCO = CLK / (n + 1).

This function sets the clock

source for the CCO clock.

CLK_ADCConfig

CLK_ADC_Source specifies

the clock source for the ADC. It

can be one of the following

peripherals: HSI, PLL, LSI,

HSE.

CLK_ADC_DIV is the division

factor for PLL selected clock.

CLKADC = CLKSEL / (n+1).

This function sets the clock

source for the ADC.

CLK_AWUConfig

CLK_AWU_DIVIDER is the

division factor for the AWU

clock. It can be a power of two

ranging from 1 to 256.

This function configures the

AWU clock.

CLK_SMEDConfig

CLK_SMD selects the SMEDx

clock to be configured.

Source specifies the clock

source for the SMEDx. It can be

one of the following peripherals:

HSI, PLL, LSI, HSE.

Prescaler is the division factor

for the SMEDx clock. It can be

a power of two ranging from

1 to 128.

This function configures the

SMEDS clock.

Table 2. STLUX385A clock (continued)

Header

Input parameters

Output

parameters

Functionality

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