AN421

Software description

Doc ID 2476 Rev 2

7/11

3.2

Timer/watchdog programming

As an example, the Timer Watchdog is initialized in order to provide a time base of 10 ms

(with a ST9 driven by a clock frequency of 24 MHz internally divided by two). To enable the

Watchdog mode, the requirement is to initialize Timer prescaler and counter, to initialize the

Timer/Watchdog Control Register with its reset value, and then to enable the watchdog

mode by clearing the WDGEN bit in the Wait Control Register in page 0. Resetting this bit

causes the counter to start in Watchdog mode regardless of the start/stop,

Single/Continuous and input mode bits.

Figure 3.

Timer/watchdog initialization

Note:

1

A bit (DIV2 located in the MODE Register MODER, R235 in the system group) controls the

divide by two circuit which operates on the OSCIN clock driving the ST9. The maximum

Internal Clock (INTCLK) allowable for the ST9 is 12 MHz. This internal clock drives all the

ST9 peripherals, while this same clock, optionally slowed down by the ST9 Core clock

programmable prescaler and by wait cycle insertion, drives the ST9 Core. After a reset

cycle, the clock frequency applied to the ST9 is divided by two and no Core clock prescaling

is done.

3.3

Timer/Watchdog restart

This example shows how to restart the Timer Watchdog when the stack is located in

Register File or in RAM space. In the register file, the two instructions:

ld WDTLR,#END_SSTACK-2

ld WDTLR,#END_SSTACK-1

load the restart value of Timer Watchdog.

;***************************************************************

**

; WATCHDOG INITIALISATION

;***************************************************************

**

proc INIT_WGT[PPR] {

spp #0

ld WDTPR,#0

; TWD prescaler register

ld WDTLR,#-30h

;

; TWD Timer counter low

ld WDTHR,#075h

;

; TWD Timer counter high

}

call INIT_WGT

; call TWD initialisation

spp #0

;

; select page 0 register

ld WCR,#00111111b

;

; Enable the Watchdog

ei

;

; Enable Interrupt