AN440 datasheet(4/8 Pages) STMICROELECTRONICS

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Gate current pulse width setting

AN440

4/8

t1 calculation

The TRIAC gate has to be supplied to reach an anode current higher than the latching

current. Furthermore, a minimum gate current pulse width of 20 µs has to be ensured. The

minimum t1 level is then given by the following equation:

Where

ω = 2.π.f and f is mains frequency.

IRMS: minimum rms current of the load (depending on line and load variations).

Figure 4 shows the minimum time versus IRMS load current for a 50Hz application.

Figure 4.

t1 time versus IRMS for different load currents (worst case: ILQ2)

Note:

Curve given for VCE = 1 V and VGK = 1.3 V

IGT is the maximum gate trigger current specified in the data sheet. To ensure a good safety

margin and a good triggering we chose IGM = 2.IGT.

The gate resistor can be defined by the following equation:

with typically VCE = 1 V and VGK = 1.3 V at IGM = 2.IGT

Capacitor C is then given by the following equation (where t1 is given by Figure 4):

Figure 5 gives the minimum capacitance versus supply voltage for different TRIACs series.

To ensure that capacitor C will be charged for the nest half cycle, R2 could be chosen with

this equation (charging time constant < 1 ms):

20 µs

asin

RMS

MAX

⎟

⎠

⎞

⎜

⎝

⎛

≥

100

120

140

160

180

200

0123456789

10 11 12 13 14 15 16 17 18 19 20

IT(rms) (A)

t1 (µs)

BW SERIES

CW SERIES

t1 (CW -> 60mA)

t1 (BW -> 80mA)

()

·ln

≥

0.001

R 2 <

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