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ST62 in-circuit programming

Application design guidelines

Some care has to be taken in the application de-

sign in order to be compatible with the in-circuit

programming capability.

1) The OSCin pin is used to synchronize the pro-

gramming operations with a clock sent by the pro-

gramming tool through the 16 wire cable. This

node must be directly tied to the relevant pin of the

16 wire cable. No isolation is needed as long as a

quartz crystal or a ceramic resonator is used in the

application. If an external clock generator is used

in the application, it has to be disconnected during

the in-circuit programming operation.

2) The RESET pin is used by the programming

tool to control the programming mode entry. Then

a direct connection to the device, and a correct

isolation from other signals of the application is

mandatory to prevent any voltage contention. It

means that a direct connection to VDD, GND or

any other signal has to be avoided. On the contra-

ry, these pins can be connected to another CMOS

input, a 2 Kohms pull-up or left open (Internal pull-

up). The capacitive load on the RESET pin should

not exceed 1F.

3) The pin 1 and 7 of the 16 wire cable are used to

establish the communication between the pro-

gramming tool and the device. Then a direct con-

nection to the device, and a correct isolation from

other nodes of the application is mandatory to pre-

vent any voltage contention. It means that any di-

rect connection to VDD, GND or an output has to

be avoided. On the contrary, these pins can be

connected to a CMOS input, a 2 Kohms pull-up, a

10Kohms pull-down or left open (Internal pull-up).

If the pin 3 of the 16 pin connector is tied to the

ST62 MCU, the same concerns apply. 4) Some

I/O pins are not connected to the 16 wire cable

and must be set at high level during the program-

ming operation. This is normally achieved by the

RESET signal sent by the programming tool

through the 16 wire cable, setting the I/O lines as

input with an internal 300 Kohms pull-up. In order

to keep at high level these I/O lines, a direct con-

nection of these pins to GND or to any other signal

at low (even temporarily) voltage level has to be

avoided. Only connections to another CMOS in-

put, an external pull-up or a 10 MOhms pull down

is allowed.

The following table summarizes the signal to be

kept at high voltage level.

*: If not directly biased through the pin 3 of the 16

pin connector.

5) The pin Vpp/TM can not be directly tied to GND

on the application in order to do not conflict with

the biasing issued by the programming tool

through the pin 13 of the connector. Instead it

should be pulled down by a resistor with a mini-

mum value of 10 Kohms. It is also mandatory to

add a 100nF ceramic capacitor between Vpp/TM

and Vss.

ST621X/2X

ST624X

ST626X

ST628X

PB3

PB0

PB6

PB3

PB5 *

PA5 *

PB0 *

PC5*