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PWM GENERATION WITH THE ST62 16-BIT AUTO-RELOAD TIMER

2 PULSE WIDTH MODULATION (PWM) GENERATION

Using the PWM generation capability of the ARTimer, the CPU of the microcontroller has only

to start/stop the timer and update the duty cycle. High speed PWM signals in the range of up

signal period is controlled by the Reload register RLCP. The duty cycle is defined by the Com-

pare register CMP (see Figure 2.).

The TC register is decremented from the RLCP value to 0, then reloaded at the RLCP value

to decrement again. The PWM output is set or reset or toggled when MASK&TC=0 (de-

pending on the PWMPOL bit of the SCR4 register and the PWMMD bit of the SCR3 register)

and is reset or set or toggled when MASK&TC=MASK&CMP.

The CMP register can have any value between the RLCP value and 0, but in PWM mode, this

CMP register value should not be equal to zero.

So the RLCP value should be as high as possible, the MASK value equal to FFFFh and the

prescaler ratio as low as possible to achieve maximum resolution.

Major equations for PWM generation are:

With PWMPOL=0

Duty cycle: (RLCP-CMP) / (RLCP+1)

With PWMPOL=1

Duty cycle: (CMP+1) / (RLCP+1)

Resolution: 1 / (RLCP+1)

With a 8 MHz oscillator and a prescaler ratio of 1, the maximum resolution (1/(RLCP=FFFFh))

order gives an analog output equivalent to a 16 bit DAC!

Table 1. Prescaler Programming Ratio

PSC2

PSC1

PRESCALER Ratio

0

0

Clock Disabled

01

1

10

4

11

16