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AN971 数据表(PDF) 4 Page - STMicroelectronics |
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AN971 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 7 page ![]() 4/7 I2C COMMUNICATION BETWEEN ST7 AND M24Cxx EEPROM 2.4 INITIATING A COMMUNICATION ON THE I2C BUS To initiate an I2C communication, first a start condition has to be generated and then the se- lected slave address has to be sent, both by the master. In the ST7 I2C peripheral this action is done by setting the START bit of the Control Register (CR) followed by writing the slave address in the Data Register (DR) with the least significant bit correctly set (0 = transmission, 1 = reception). 2.5 SENDING A DATA BYTE ON THE I2C BUS To transmit a new data byte from the ST7 I2C peripheral on the I2C bus, the address or data byte previously transmitted has to be completed correctly. This previous byte transmission check is done by a polling loop on the BTF flag of the Status Register 1 (SR1). If during this loop an error is detected in the Status Registers (SR1,SR2) then the application goes into an infinite loop (no error management). When the previous data transmission is over, the application writes the new data byte to be transmitted in the Data Register (DR). Note: If the data byte to be transmitted is the first one after the slave address, a dummy write in the Control Register (CR) has to be performed to allow the setting of the BTF bit (see ST7 datasheet for more details). In this application, this dummy write is done by setting the PE bit for each data byte transmission (see description of EV6 in the Transfer Sequencing diagram in I2C datasheet description). 2.6 RECEIVING A DATA BYTE ON THE I2C BUS To receive a new data byte in the ST7 I2C peripheral from the I2C bus, the data byte to receive has to be completed correctly. This byte reception check is done by a polling loop on the BTF flag of the Status Register 1 (SR1). If during this loop an error is detected in the Status Regis- ters (SR1, SR2) then the application goes in an infinite loop (no error management). When the data reception is finalized, the application reads the new data byte received in the Data Register (DR). To close the communication: Before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/ SL bit cleared). In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Note: If the data byte to be received is the first one after the slave address, a dummy write in the Control Register (CR) has to be performed to allow the setting of the BTF bit (see ST7 da- tasheet for more details). In this application, this dummy write is done by setting the PE bit for each data byte reception (see description of EV6 in the Transfer Sequencing diagram in I2C datasheet description). |
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