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AN1014 数据表(PDF) 5 Page - STMicroelectronics |
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AN1014 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 25 page ![]() 5/25 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION 3.4 SLOW WAIT MODE In this mode, the CPU is stopped and the peripherals are still running at the fCPU defined for SLOW mode. It is activated when entering WAIT mode while the device is already in SLOW mode. Uses: - To place the MCU simultaneously in Slow mode and Wait mode to reduce the power con- sumption. 3.5 ACTIVE-HALT MODE In this mode, the CPU and the peripherals are stopped, but the oscillator is still running. Pe- ripherals clocked with an external clock source can still be active. It is selected by calling the “HALT” instruction when the MCCSR - OIE bit is set. “HALT” forces the I[1:0] bits in the CC register to ‘10’ to enable interrupts. The CPU clock is stopped till a Reset or MCC/RTC or CSS or other specific interrupt occurs. To wake-up from ACTIVE-HALT, a Reset or MCC/RTC or CSS or other specific interrupt must occur. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set to the current software priority level of the interrupt routine and recov- ered when the CC register is popped. The safeguard against staying locked in ACTIVE-HALT mode is provided by the oscillator interrupt. As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. Be- cause the watchdog remains active, this means that the MCU cannot spend more than a de- fined delay in ACTIVE-HALT mode. Uses: - To place the MCU in the lowest power consumption mode with Real Time Clock available. - The CPU and Peripherals (Peripheral clocked with external clock source can still be active) are OFF. - To keep a wake-up time base, the Real Time Clock Main Clock Controller is running. 3.6 HALT MODE In this mode, the oscillator is turned off. Peripherals clocked with an external clock source can still be active. Halt mode is selected by calling a “HALT” Instruction while the MCCSR - OIE bit is cleared. “HALT” forces the I[1:0] bits in the CC register to ‘10’ to enable interrupts. The CPU clock is stopped till a Reset or a specific interrupt (with “exit from Halt” capability) oc- curs. To wake-up the MCU from Halt mode (when the Watchdog is active or when the |
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