LTC1663

5

1663fd

TYPICAL PERFORMANCE CHARACTERISTICS

Load Regulation vs Output Current

Offset Error Voltage vs

Temperature

Full-Scale Output Voltage vs

Temperature

–1.0

–1.0

–0.8

–0.4

–0.2

0

1.0

0.4

–0.6 –0.4

0

0.2

1663 G07

–0.6

0.6

0.8

0.2

–0.8

–0.2

0.6

0.4

0.8 1.0

CODE = 512

SOURCE

SINK

TEMPERATURE (°C)

–60

5

4

3

2

1

0

–1

–2

–3

–4

–5

–20

20

40

1663 G08

–40

0

60

80

100

TEMPERATURE (°C)

–60

2.510

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

–20

20

40

1663 G09

–40

0

60

80

100

REFERENCE SET TO

INTERNAL BANDGAP

SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional

Pin. Data is shifted into the SDA pin and acknowledged

by the SDA pin. High impedance pin while data is shifted

in. Open-drain N-channel output during acknowledgment.

AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to

LTC1663’s slave address.

AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to

LTC1663’s slave address.

SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin.

Data is shifted into the SDA pin at the rising edges of the

clock. This high impedance pin requires a pull-up resistor

≤ 5.5V. Also used as the reference voltage input when the

AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to

LTC1663’s slave address.

GND (Pin 7, Pin 2 on SOT-23): System Ground.

rail-to-rail DAC output.

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

two adjacent codes. The DNL error between any two codes

is calculated as follows:

two adjacent codes.

Digital Feedthrough: The glitch that appears at the ana-

log output caused by AC coupling from the digital inputs

when they change state. The area of the glitch is specified

in (nV)(sec).

Full-Scale Error (FSE): The deviation of the actual full-scale

voltage from ideal. FSE includes the effects of offset and

gain errors (see Applications Information).

DEFINITIONS

PIN FUNCTIONS