| 数据搜索系统,热门电子元器件搜索 |
|
AN1048 数据表(PDF) 13 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN1048 数据表(HTML) 13 Page - STMicroelectronics |
|
13 / 21 page ![]() AN1048 Example of a quadruplex LCD with ST72F321B 13/21 Active time starts after the Output Compare 1 interrupt and dead time starts after the Output Compare 2 interrupt. A total of 16 interrupts are generated in each frame period with four interrupts per control period. There are 2 Output Compare 1 events (OC1_1 and OC1_2) and 2 Output Compare 2 events in each phase.These are explained as follows: During OC1_1, VDD is applied to the segments which have to be turned ON and 0 for the segments which have to be turned OFF. The COM line which corresponds to this phase is set to low level. Other COM lines are set to level VDD/2. During OC2, all segments and COM lines are inactive (set to low level) if we want to decrease the Vrms (see Figure 9) and COM lines are set low, segments are set high if we want to increase the Vrms (see Figure 10). During OC1_2, Segment Lines are supplied with voltage levels which are inverted to the one applied during OC1_1.COM line which corresponds to this phase is set to high level.Other COM lines are set to level VDD/2. Again during OC2, all segments and COM lines are inactive(set to low level) if we want to decrease the Vrms and COM lines are set high, segments are set low if we want to increase the Vrms (see Figure 10). |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |