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MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B

4.1.3 Option Byte and Miscellaneous Register Programming

Table 3. ST7263B Configuration for ST7263 Rev.B Upward Compatibility

Table 4. Internal Frequency Configuration

4.2 PERIPHERALS

The I²C and USB peripherals are fully software compatible as long as the application software

has been recompiled with an updated register map.

4.2.1 Serial Communications Interface (SCI) (Not upward compatible)

Certain new features such as the power down and parity generation/check functions have

been added and are controlled by bits that were unused on the ST7263 Rev. B. As long as the

following 5 bits are set to 0 on the ST7263 Rev.B software, they are directly upward compat-

ible when recompiled with an updated register map.

The new parity management feature in the ST7263B requires the following configuration in

both Transmission and Reception modes:

In the SCICR1 register,

– Bit 5 = SCID SCI Disabled

When this bit is set, the SCI cell is disabled and power consumption is reduced.

– Bit 2 = PCE Parity Control Enable

Select the hardware parity control. In transmission, parity is inserted at the MSB position,

and parity is checked in Reception mode.

– Bit 1 = PS Parity Selection

Even (0) or Odd (1)

– Bit 0 = PIE Parity Interrupt Enable

Generates an interrupt when a parity error is detected.

ST7263 Rev. B

Configuration

Equivalent ST7263B Configuration

LVD

(MISCR)

CLKDIV

(MISCR)

SMS

(MISCR)

Option Byte

WDGSW

LVD

OSC24/12

WDHALT

FMP_R

0

0

0

1

0

0

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

1

1

1

0

1

1

1

0

1

Quartz

OSC24/12

Option Byte (Bit 1)

Slow Mode

MISCR (Bit 2)

24 MHz

0

0

8 MHz

6 MHz

24 MHz

0

1

4 MHz

6 MHz

12 MHz

1

0

4 MHz

6 MHz

12 MHz

1

1

2 MHz

6 MHz