2/3

USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION

2.2 SPI OVERRUN FLAG

Description: On the ST72521 emulator chip cut 1.3, some overrun errors cannot be detected

during status register clearing phase. This behavior has been solved on the ST72324.

Impact on Software: The overrun condition cannot be debugged on this version of the emu-

lator. No impact on software.

2.3 IC2 AND OC2 ON TIMER A

Description: In the ST72324, the IC2 and OC2 functions are not available on Timer A. They

are available in the ST72521.

Impact on Software:

1. The OC2HR, OC2LR, IC2HR, IC2LR registers must not be accessed (except for the action in item 6 of

this list).

2. The FOLV2 and OLVL2 control bits in the CR1 register must be kept cleared.

3. The OC2E and IEDG2 control bits in the CR2 register must be kept cleared.

4. The ICF2 and OCF2 flag values must not be taken into account by the software (meaningless).

5. Timer A PWM mode must not be used: The PWM control bit in the CR2 register must be kept cleared.

The generated PWM signal would be different on the ST72521 and ST72324.

6. A dummy read to the OC2LR and IC2LR registers has to be performed at the end of the Timer A inter-

rupt routine to discard the OC2 and IC2 interrupts that can occur on the ST72521 but not on the

ST72324.

3 ST72521 CUT 1.6 VERSUS ST72324 CUT 1.0

3.1 IC2 AND OC2 ON TIMER A

Description: In the ST72324 the IC2 and OC2 functions are not available on Timer A. They

are available in the ST72521.

Impact on Software:

1. The OC2HR, OC2LR, IC2HR, IC2LR registers must not be accessed (except for the action in item 6 of

this list).

2. The FOLV2 and OLVL2 control bits in the CR1 register must be kept cleared.

3. The OC2E and IEDG2 control bits in the CR2 register must be kept cleared.

4. The ICF2 and OCF2 flag values must not be taken into account by the software (meaningless).

5. Timer A PWM mode must not be used: The PWM control bit in the CR2 register must be kept cleared.

The generated PWM signal would be different on the ST72521 and ST72324.

6. A dummy read to the OC2LR and IC2LR registers has to be performed at the end of the Timer A inter-

rupt routine to discard the OC2 and IC2 interrupts that can occur on the ST72521 but not on the

ST72324.